WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores¶
This specification is maintained by Richard Herveille (firstname.lastname@example.org) and hosted by the Free and Open Source Silicon Foundation. Questions, comments and suggestions about this document are welcome and should be directed to the mailing list (https://lists.librecores.org/listinfo/discussion) and the GitHub repository (https://github.com/fossi-foundation/wishbone).
These specifications are intended to guarantee compatibility between compliant IP-cores and to improve cooperation among different users and suppliers.
Copyright & Trademark Release / Royalty Release / Patent Notice
Notice is hereby given that this document is not copyrighted, and has been placed into the public domain. It may be freely copied and distributed by any means.
The name ‘WISHBONE’ and the ‘WISHBONE COMPATIBLE’ rubber stamp logo are hereby placed into the public domain (within the scope of System-on-Chip design, System-on-Chip fabrication and related areas of commercial use). The WISHBONE logo may be freely used under the compatibility conditions stated elsewhere in this document.
This specification may be used for the design and production of System-on-Chip (SoC) components without royalties or other financial obligations to FOSSi Foundation, OpenCores or any other party.
The author(s) of this specification are not aware that the information contained herein, nor of products designed to the specification, cause infringement on the patent, copyright, trademark or trade secret rights of others. However, there is a possibility that such infringement may exist without their knowledge. The user of this document assumes all responsibility for determining if products designed to this specification infringe on the intellectual property rights of others.
In no event shall OpenCores or any of the contributors be liable for any direct, indirect, incidental, consequential, exemplary, or special damages (including, but not limited to procurement of substitute goods or services; loss of use, data, or profits; or business interruption) resulting in any way from the use of this specification. By adopting this specification, the user assumes all responsibility for its use.
This is a preliminary document, and is subject to change.
Verilog® is a registered trademark of Cadence Design Systems, Inc.
Like any great technical project, the WISHBONE specification could not have been completed without the help of many people. The Steward wishes to thank the following for their ideas, suggestions and contributions:
Wade D. Peterson 1
Wade D. Peterson from Silicore Corporation is the original author and steward. Without his dedication this specification would have never been where it is now.
This specification is managed at the following repository: https://github.com/fossi-foundation/wishbone
- Interface Specification
- WISHBONE Classic Bus Cycle
- WISHBONE Registered Feedback Bus Cylces
- Timing Specification
- Cited Patent References